Subject description
The aim of this subject is to provide students with the knowledge of current computer architecture and the skill to design and interface an RISC processor. The topics covered include processor data path and control, CPU architecture, performance issues, enhancing performance through pipelining, memory hierarchy, Cache, DMA, Buses and other … For more content click the Read More button below.
Enrolment rules
Co-Requisite
Pre-Requisite
Equivalence
ECTE491 - Computer Architectures
Delivery
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Learning outcomes
On successful completion of this subject, students will be able to:
1.
Explain the principles of the organisation, operation and design of Complex Instruction Set and Reduced Instruction Set Computers and their control units.
2.
Explain the principles of system design, with particular emphasis on interconnection and I/O structures.
3.
Design interfacing circuitry between microprocessors and real-world signals.
4.
Design an efficient cache system.
5.
Demonstrate appropriate practical and problem solving skills.
Assessment details
Tutorial Quizzes
Laboratory project report
In class tests
Laboratory progressive project assessment
Textbook information
No prescribed textbooks for this subject.